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| author |   Kevin Wang <kevin1.wang@amd.com> | 2019-10-11 08:45:41 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-10-15 15:48:37 -0400 |
| commit | 4e71e0859292f96d4124805c4e02ef34366451b9 (patch) | |
| tree | 0bd09ace4004ab606a4da47e5216c66015bb3819 /drivers/gpu/drm/amd/powerplay/navi10_ppt.h | |
| parent | drm/amd/powerplay: enable df cstate control on swSMU routine (diff) | |
| download | linux-dev-4e71e0859292f96d4124805c4e02ef34366451b9.tar.xz linux-dev-4e71e0859292f96d4124805c4e02ef34366451b9.zip | |
drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14
add navi14 umd pstate peak clock support.
NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz
NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz
NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz
NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz
NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/navi10_ppt.h')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h index 620ff17c2fef..a37e37c5f105 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h @@ -27,6 +27,12 @@ #define NAVI10_PEAK_SCLK_XT (1755) #define NAVI10_PEAK_SCLK_XL (1625) +#define NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK (1670) +#define NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK (1448) +#define NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK (1181) +#define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717) +#define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448) + extern void navi10_set_ppt_funcs(struct smu_context *smu); #endif |