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| author |   Jimmy Kizito <Jimmy.Kizito@amd.com> | 2021-04-19 15:12:01 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-06-08 12:19:34 -0400 |
| commit | 0cb1588571a7ba42108f913d0938a3a03a698027 (patch) | |
| tree | ec6b57ede544fab4f0850b3925869ddb8c60636f /drivers/gpu/drm/amd | |
| parent | drm/amd/display: Revert "Fix clock table filling logic" (diff) | |
| download | linux-dev-0cb1588571a7ba42108f913d0938a3a03a698027.tar.xz linux-dev-0cb1588571a7ba42108f913d0938a3a03a698027.zip | |
drm/amd/display: Expand DP module equalization API.
[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 22 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 8 |
2 files changed, 19 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 5a70f55e075c..87f955820c0f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -435,7 +435,7 @@ bool dp_is_cr_done(enum dc_lane_count ln_count, return true; } -static bool is_ch_eq_done(enum dc_lane_count ln_count, +bool dp_is_ch_eq_done(enum dc_lane_count ln_count, union lane_status *dpcd_lane_status) { bool done = true; @@ -446,7 +446,7 @@ static bool is_ch_eq_done(enum dc_lane_count ln_count, return done; } -static bool is_symbol_locked(enum dc_lane_count ln_count, +bool dp_is_symbol_locked(enum dc_lane_count ln_count, union lane_status *dpcd_lane_status) { bool locked = true; @@ -457,7 +457,7 @@ static bool is_symbol_locked(enum dc_lane_count ln_count, return locked; } -static inline bool is_interlane_aligned(union lane_align_status_updated align_status) +bool dp_is_interlane_aligned(union lane_align_status_updated align_status) { return align_status.bits.INTERLANE_ALIGN_DONE == 1; } @@ -865,9 +865,9 @@ static bool perform_post_lt_adj_req_sequence( if (!dp_is_cr_done(lane_count, dpcd_lane_status)) return false; - if (!is_ch_eq_done(lane_count, dpcd_lane_status) || - !is_symbol_locked(lane_count, dpcd_lane_status) || - !is_interlane_aligned(dpcd_lane_status_updated)) + if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) || + !dp_is_symbol_locked(lane_count, dpcd_lane_status) || + !dp_is_interlane_aligned(dpcd_lane_status_updated)) return false; for (lane = 0; lane < (uint32_t)(lane_count); lane++) { @@ -913,7 +913,7 @@ static bool perform_post_lt_adj_req_sequence( } /* Only used for channel equalization */ -static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) +uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) { unsigned int aux_rd_interval_us = 400; @@ -998,7 +998,7 @@ static enum link_training_result perform_channel_equalization_sequence( if (is_repeater(link, offset)) wait_time_microsec = - translate_training_aux_read_interval( + dp_translate_training_aux_read_interval( link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); dp_wait_for_training_aux_rd_interval( @@ -1021,9 +1021,9 @@ static enum link_training_result perform_channel_equalization_sequence( return LINK_TRAINING_EQ_FAIL_CR; /* 6. check CHEQ done*/ - if (is_ch_eq_done(lane_count, dpcd_lane_status) && - is_symbol_locked(lane_count, dpcd_lane_status) && - is_interlane_aligned(dpcd_lane_status_updated)) + if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && + dp_is_symbol_locked(lane_count, dpcd_lane_status) && + dp_is_interlane_aligned(dpcd_lane_status_updated)) return LINK_TRAINING_SUCCESS; /* 7. update VS/PE/PC2 in lt_settings*/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index bbb054f58fe2..883c3af51022 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -130,6 +130,12 @@ bool dp_is_cr_done(enum dc_lane_count ln_count, enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, union lane_status *dpcd_lane_status); +bool dp_is_ch_eq_done(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status); +bool dp_is_symbol_locked(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status); +bool dp_is_interlane_aligned(union lane_align_status_updated align_status); + bool dp_is_max_vs_reached( const struct link_training_settings *lt_settings); @@ -137,6 +143,8 @@ void dp_update_drive_settings( struct link_training_settings *dest, struct link_training_settings src); +uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval); + enum dpcd_training_patterns dc_dp_training_pattern_to_dpcd_training_pattern( struct dc_link *link, |