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| author |   Arnd Bergmann <arnd@arndb.de> | 2017-04-25 21:56:53 +0200 |
|---|---|---|
| committer |   Liviu Dudau <Liviu.Dudau@arm.com> | 2017-04-26 17:54:58 +0100 |
| commit | 763656d30b3d220a52e4b2bd1fc174a4cd6c0f43 (patch) | |
| tree | ea546747872e054429aab11defc21a0987ccd898 /drivers/gpu/drm/arm | |
| parent | drm: mali-dp: Check the mclk rate and allow up/down scaling (diff) | |
| download | linux-dev-763656d30b3d220a52e4b2bd1fc174a4cd6c0f43.tar.xz linux-dev-763656d30b3d220a52e4b2bd1fc174a4cd6c0f43.zip | |
drm: mali-dp: use div_u64 for expensive 64-bit divisions
On 32-bit machines, we can't divide 64-bit integers:
drivers/gpu/drm/arm/malidp_crtc.o: In function `malidp_crtc_atomic_check':
malidp_crtc.c:(.text.malidp_crtc_atomic_check+0x3c0): undefined reference to `__aeabi_uldivmod'
malidp_crtc.c:(.text.malidp_crtc_atomic_check+0x3dc): undefined reference to `__aeabi_uldivmod'
This calls the div_u64 function explicitly instead.
Fixes: 4cea4e9f6690 ("drm: mali-dp: Add plane upscaling support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/gpu/drm/arm')
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_crtc.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index 19f1f3b34691..9446a673d469 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -266,7 +266,6 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { struct malidp_plane *mp = to_malidp_plane(plane); - u64 crtc_w, crtc_h; u32 phase; if (!(mp->layer->id & scaling)) @@ -276,10 +275,10 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h] * to get the U16.16 result. */ - crtc_w = (u64)pstate->crtc_w << 32; - crtc_h = (u64)pstate->crtc_h << 32; - h_upscale_factor = (u32)(crtc_w / pstate->src_w); - v_upscale_factor = (u32)(crtc_h / pstate->src_h); + h_upscale_factor = div_u64((u64)pstate->crtc_w << 32, + pstate->src_w); + v_upscale_factor = div_u64((u64)pstate->crtc_h << 32, + pstate->src_h); s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 || (v_upscale_factor >> 16) >= 2); |