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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-05-06 14:28:57 +0300 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-08 13:03:43 +0200 |
| commit | 22e02c0b4bc87c94895b1f4cb25ee705d5687cb1 (patch) | |
| tree | d48165d237c6afd2e74b6e5c0b585382cfbb9a9f /drivers/gpu/drm/drm_edid.c | |
| parent | drm/i915: s/9/intel_freq_opcode(450)/ (diff) | |
| download | linux-dev-22e02c0b4bc87c94895b1f4cb25ee705d5687cb1.tar.xz linux-dev-22e02c0b4bc87c94895b1f4cb25ee705d5687cb1.zip | |
drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/drm_edid.c')
0 files changed, 0 insertions, 0 deletions