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| author |   Stefan Agner <stefan@agner.ch> | 2016-10-05 14:37:57 -0700 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2016-10-19 17:02:59 -0700 |
| commit | 9789037695018e25902469ea0e540c07580b940f (patch) | |
| tree | 14d5dc8e8eaff89dc4c1bb2421dcaee633047f48 /drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | |
| parent | drm/fsl-dcu: do not transfer registers on plane init (diff) | |
| download | linux-dev-9789037695018e25902469ea0e540c07580b940f.tar.xz linux-dev-9789037695018e25902469ea0e540c07580b940f.zip | |
drm/fsl-dcu: do not transfer registers in mode_set_nofb
Do not schedule a transfer of mode settings early. Modes should
get applied on on CRTC enable where we also enable the pixel clock.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-By: Meng Yi <meng.yi@nxp.com>
Diffstat (limited to 'drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index 3371635cd4d7..5ad1d68c8194 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); - regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, - DCU_UPDATE_MODE_READREG); return; } |