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| author |   Tian Tao <tiantao6@hisilicon.com> | 2019-12-31 14:42:51 +0800 |
|---|---|---|
| committer |   Xinliang Liu <xinliang.liu@linaro.org> | 2020-02-27 04:34:31 +0000 |
| commit | bac511833da98ebffa342f790f66f2df0b964f3c (patch) | |
| tree | 06c5a10c562b6052cb3180d637a23ecf6cade05c /drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | |
| parent | drm/omap: dss: Remove unused omap_dss_device operations (diff) | |
| download | linux-dev-bac511833da98ebffa342f790f66f2df0b964f3c.tar.xz linux-dev-bac511833da98ebffa342f790f66f2df0b964f3c.zip | |
drm/hisilicon: Add new clock/resolution configurations
Add the three new pll config for corresponding resolution 1440x900 and
1600x900, 640x480 for hibmc
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Gong junjie <gongjunjie2@huawei.com>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1577774571-60493-1-git-send-email-tiantao6@hisilicon.com
Diffstat (limited to 'drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c')
| -rw-r--r-- | drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c index 561b398ca93d..66ed6b0441e6 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -40,6 +40,7 @@ struct hibmc_dislay_pll_config { }; static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { + {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, @@ -47,6 +48,8 @@ static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, + {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, |