diff options
| author |   Imre Deak <imre.deak@intel.com> | 2020-02-26 22:34:48 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2020-03-02 19:36:21 +0200 |
| commit | 45e4728b87ad03b3f9a0babe04cadef90c63291d (patch) | |
| tree | 77dcf4d150a2270a6158e94ce72bb0dcb3e9d38e /drivers/gpu/drm/i915/display/icl_dsi.c | |
| parent | drm/i915/hsw: Use the DPLL ID when calculating DPLL clock (diff) | |
| download | linux-dev-45e4728b87ad03b3f9a0babe04cadef90c63291d.tar.xz linux-dev-45e4728b87ad03b3f9a0babe04cadef90c63291d.zip | |
drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
Move all the DPLL params->DPLL frequency conversion functions to
intel_dpll_mgr.c where the corresponding inverse conversions are.
The GEN11+ TBT PLL outputs multiple frequencies and for selecting the
one in use we need to check the DDI CLK mux. As part of the DDI clock
logic this selection is kept in intel_ddi.c.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-7-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/icl_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/icl_dsi.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index c7214ace963a..c38addd07e42 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1350,15 +1350,13 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); intel_dsc_get_config(encoder, pipe_config); /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ - pipe_config->port_clock = - cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); + pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config); pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; if (intel_dsi->dual_link) |