diff options
| author |   Vandita Kulkarni <vandita.kulkarni@intel.com> | 2019-12-10 12:50:59 +0200 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2019-12-11 08:19:49 +0200 |
| commit | c2bb35e99f4b426efdd28011655bd67ca86749b5 (patch) | |
| tree | 6ca414701dd8028b834baf3a3d0efc6d7b06d01b /drivers/gpu/drm/i915/display/icl_dsi.c | |
| parent | drm/i915/dsi: account for DSC in horizontal timings (diff) | |
| download | linux-dev-c2bb35e99f4b426efdd28011655bd67ca86749b5.tar.xz linux-dev-c2bb35e99f4b426efdd28011655bd67ca86749b5.zip | |
drm/i915/dsi: Fix state mismatch warns for horizontal timings with DSC
When DSC is enabled consider the compression ratio that was used during
horizontal timing calculations.
This may still lead to warns due to rounding errors in the round-trip.
v2 by Jani:
- rebase on top of the more generic dsc state readout
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c2481aaf67ea396aa4698cd2d8e23d19ec4f4ecf.1575974743.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/icl_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/icl_dsi.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index caa477c4b1af..b1d775d834d4 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1255,6 +1255,18 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + if (pipe_config->dsc.compressed_bpp) { + int div = pipe_config->dsc.compressed_bpp; + int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); + + adjusted_mode->crtc_htotal = + DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); + adjusted_mode->crtc_hsync_start = + DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); + adjusted_mode->crtc_hsync_end = + DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); + } + if (intel_dsi->dual_link) { adjusted_mode->crtc_hdisplay *= 2; if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |