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authorAnusha Srivatsa <anusha.srivatsa@intel.com>2021-06-21 12:14:13 -0700
committerAnusha Srivatsa <anusha.srivatsa@intel.com>2021-06-21 16:15:27 -0700
commit3d5928a168a9546b23c6b3439c6158d7a028326c (patch)
treecafa50960081630c69ed35ac23039f8dcf63b4b1 /drivers/gpu/drm/i915/display/intel_dmc.h
parentdrm/i915/dmc: Introduce DMC_FW_MAIN (diff)
downloadlinux-dev-3d5928a168a9546b23c6b3439c6158d7a028326c.tar.xz
linux-dev-3d5928a168a9546b23c6b3439c6158d7a028326c.zip
drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already existing parsing and loading functions which is taken care of in the prep patches. Adding MAX_DMC_FW to keep track for both Main and Pipe A DMC while loading the respective blobs. Also adding present field in dmc_info. s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add fw_info_matches_stepping() helper. CSR_PROGRAM() should now take the starting address of the particular blob (Main or Pipe) and not hardcode it. v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct. v3: Add a missing corner cases of stepping-substepping combination in fw_info_matches_stepping() helper. v4: Add macro for start_mmioaddr for V1 package. Simplify code in dmc_set_fw_offset (Lucas) Cc: Souza, Jose <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210621191415.29823-3-anusha.srivatsa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dmc.h')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dmc.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index b872f3a4fd03..007a284b0ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -18,6 +18,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
+ DMC_FW_PIPEA,
DMC_FW_MAX
};
@@ -31,8 +32,11 @@ struct intel_dmc {
u32 mmio_count;
i915_reg_t mmioaddr[20];
u32 mmiodata[20];
+ u32 dmc_offset;
+ u32 start_mmioaddr;
u32 dmc_fw_size; /*dwords */
u32 *payload;
+ bool present;
} dmc_info[DMC_FW_MAX];
u32 dc_state;