diff options
| author |   Matt Roper <matthew.d.roper@intel.com> | 2021-07-21 15:30:37 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-22 09:29:20 -0700 |
| commit | 87fc875a2b85043f9cc34f84e1beb2ec51a9e5d3 (patch) | |
| tree | 0b23f9cc9d898bb0dfcb822182494a459f5cf643 /drivers/gpu/drm/i915/display/intel_dpll_mgr.c | |
| parent | drm/i915/dg2: Add cdclk table and reference clock (diff) | |
| download | linux-dev-87fc875a2b85043f9cc34f84e1beb2ec51a9e5d3.tar.xz linux-dev-87fc875a2b85043f9cc34f84e1beb2ec51a9e5d3.zip | |
drm/i915/dg2: Skip shared DPLL handling
DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded
within the PHY.
Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-13-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 9b5324d015ec..d180aec4e530 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4462,7 +4462,10 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (IS_ALDERLAKE_P(dev_priv)) + if (IS_DG2(dev_priv)) + /* No shared DPLLs on DG2; port PLLs are part of the PHY */ + dpll_mgr = NULL; + else if (IS_ALDERLAKE_P(dev_priv)) dpll_mgr = &adlp_pll_mgr; else if (IS_ALDERLAKE_S(dev_priv)) dpll_mgr = &adls_pll_mgr; |