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authorJani Nikula <jani.nikula@intel.com>2022-01-19 13:05:28 +0200
committerJani Nikula <jani.nikula@intel.com>2022-01-19 15:03:50 +0200
commitd39bc5c5e10a648c7de9558592816474f45a374d (patch)
treea54a570896b9db67eb6eadde9037653c6b4421b8 /drivers/gpu/drm/i915/display/intel_dpll_mgr.c
parentdrm/i915: Nuke pointless middle men for skl+ plane programming (diff)
downloadlinux-dev-d39bc5c5e10a648c7de9558592816474f45a374d.tar.xz
linux-dev-d39bc5c5e10a648c7de9558592816474f45a374d.zip
drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.c
Move struct intel_shared_dpll_funcs to intel_dpll_mgr.c, as no other place needs to have access to it. We also don't need to have kernel-doc documentation for file internal structures, so drop them while at it. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220119110528.2377899-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dpll_mgr.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3f7357123a6d..6723c3de5a80 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -50,6 +50,41 @@
* commit phase.
*/
+/* platform specific hooks for managing DPLLs */
+struct intel_shared_dpll_funcs {
+ /*
+ * Hook for enabling the pll, called from intel_enable_shared_dpll() if
+ * the pll is not already enabled.
+ */
+ void (*enable)(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll);
+
+ /*
+ * Hook for disabling the pll, called from intel_disable_shared_dpll()
+ * only when it is safe to disable the pll, i.e., there are no more
+ * tracked users for it.
+ */
+ void (*disable)(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll);
+
+ /*
+ * Hook for reading the values currently programmed to the DPLL
+ * registers. This is used for initial hw state readout and state
+ * verification after a mode set.
+ */
+ bool (*get_hw_state)(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll,
+ struct intel_dpll_hw_state *hw_state);
+
+ /*
+ * Hook for calculating the pll's output frequency based on its passed
+ * in state.
+ */
+ int (*get_freq)(struct drm_i915_private *i915,
+ const struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *pll_state);
+};
+
struct intel_dpll_mgr {
const struct dpll_info *dpll_info;