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| author |   José Roberto de Souza <jose.souza@intel.com> | 2021-05-05 14:38:01 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-05-06 10:33:22 -0700 |
| commit | 9a5b5e1b981309179e030aca0c535a4f037dfa95 (patch) | |
| tree | 7617a9ebb874e662acb4b70eba84a8d70fdc2984 /drivers/gpu/drm/i915/display/intel_psr.c | |
| parent | drm/i915: Use intel_de_wait_for_*() in cnl+ cdclk programming (diff) | |
| download | linux-dev-9a5b5e1b981309179e030aca0c535a4f037dfa95.tar.xz linux-dev-9a5b5e1b981309179e030aca0c535a4f037dfa95.zip | |
drm/i915/display: Disable PSR2 sel fetch in TGL pre-production
The implementation of two workarounds are missing causing failures
in CI with pre-production HW.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210505213801.80772-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e3c30dcadcd1..406ba9a712a8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -720,6 +720,13 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, } } + /* Wa_14010254185 Wa_14010103792 */ + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); + return false; + } + return crtc_state->enable_psr2_sel_fetch = true; } |