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| author |   Imre Deak <imre.deak@intel.com> | 2021-09-29 16:28:33 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-09-29 23:58:11 +0300 |
| commit | b58a88682093b3438dad66f2c3d3a4d0a20ee1e8 (patch) | |
| tree | 673573ea57e1034d7ce2426b7d54c9172526b27b /drivers/gpu/drm/i915/display/intel_tc.c | |
| parent | drm/i915/tc: Drop extra TC cold blocking from intel_tc_port_connected() (diff) | |
| download | linux-dev-b58a88682093b3438dad66f2c3d3a4d0a20ee1e8.tar.xz linux-dev-b58a88682093b3438dad66f2c3d3a4d0a20ee1e8.zip | |
drm/i915/tc: Fix system hang on ADL-P during TypeC PHY disconnect
The PHY ownership release->AUX PW disable steps during a modeset
disable->PHY disconnect sequence can hang the system if the PHY
disconnect happens after disabling the PHY's PLL. The spec doesn't
require a specific order for these two steps, so this issue is still
being root caused by HW/FW teams. Until that is found, let's make
sure the disconnect happens before the PLL is disabled, and do this on
all platforms for consistency.
v2: Add a TODO comment to remove the w/a once the issue is root
caused/fixed. (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-7-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_tc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_tc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 4a14db604cba..40faa18947c9 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -834,6 +834,14 @@ void intel_tc_port_put_link(struct intel_digital_port *dig_port) intel_tc_port_lock(dig_port); --dig_port->tc_link_refcount; intel_tc_port_unlock(dig_port); + + /* + * Disconnecting the PHY after the PHY's PLL gets disabled may + * hang the system on ADL-P, so disconnect the PHY here synchronously. + * TODO: remove this once the root cause of the ordering requirement + * is found/fixed. + */ + intel_tc_port_flush_work(dig_port); } static bool |