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| author |   Matthew Brost <matthew.brost@intel.com> | 2021-07-26 17:23:33 -0700 |
|---|---|---|
| committer |   John Harrison <John.C.Harrison@Intel.com> | 2021-07-27 17:31:59 -0700 |
| commit | 573ba126aef37c8315e5bb68d2dad515efa96994 (patch) | |
| tree | 671ca22ec14a9b93c075ad9f47bc8566f68fb161 /drivers/gpu/drm/i915/gt/intel_engine_types.h | |
| parent | drm/i915/guc: Enable GuC engine reset (diff) | |
| download | linux-dev-573ba126aef37c8315e5bb68d2dad515efa96994.tar.xz linux-dev-573ba126aef37c8315e5bb68d2dad515efa96994.zip | |
drm/i915/guc: Capture error state on context reset
We receive notification of an engine reset from GuC at its
completion. Meaning GuC has potentially cleared any HW state
we may have been interested in capturing. GuC resumes scheduling
on the engine post-reset, as the resets are meant to be transparent,
further muddling our error state.
There is ongoing work to define an API for a GuC debug state dump. The
suggestion for now is to manually disable FW initiated resets in cases
where debug state is needed.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210727002348.97202-19-matthew.brost@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 1c7e2724cdae..260cce15cb62 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -298,6 +298,8 @@ struct intel_engine_cs { /* keep a request in reserve for a [pm] barrier under oom */ struct i915_request *request_pool; + struct intel_context *hung_ce; + struct llist_head barrier_tasks; struct intel_context *kernel_context; /* pinned */ |