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| author |   Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2020-05-06 17:47:32 +0300 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2020-05-07 07:44:41 +0100 |
| commit | 32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa (patch) | |
| tree | b8299959bc16a023e8b1449b5cd8d77fbe46df29 /drivers/gpu/drm/i915/gt/intel_gpu_commands.h | |
| parent | Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" (diff) | |
| download | linux-dev-32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa.tar.xz linux-dev-32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa.zip | |
drm/i915/gen12: Fix HDC pipeline flush
HDC pipeline flush is bit on the first dword of
the PIPE_CONTROL, not the second. Make it so.
v2: function naming (Chris)
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506144734.29297-2-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gpu_commands.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index b3cf09657fb2..534e435f20bc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -237,7 +237,7 @@ #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */ #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) -#define PIPE_CONTROL_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */ +#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */ #define PIPE_CONTROL_NOTIFY (1<<8) #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) |