diff options
| author |   Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2019-10-15 18:44:41 +0300 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-15 18:15:59 +0100 |
| commit | 4aa0b5d457f5d29522b5db4aeb4587fc4dc24054 (patch) | |
| tree | c8f47049dabe546301b0aae8a9d0957272e87f88 /drivers/gpu/drm/i915/gt/intel_gpu_commands.h | |
| parent | drm/i915/tgl: Include ro parts of l3 to invalidate (diff) | |
| download | linux-dev-4aa0b5d457f5d29522b5db4aeb4587fc4dc24054.tar.xz linux-dev-4aa0b5d457f5d29522b5db4aeb4587fc4dc24054.zip | |
drm/i915/tgl: Add HDC Pipeline Flush
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.
v2: Flush also in breadcrumbs (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gpu_commands.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index afc869dc785f..4294f146f13c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -235,6 +235,7 @@ #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE REG_BIT(10) /* gen12 */ #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */ #define PIPE_CONTROL_NOTIFY (1<<8) #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) |