diff options
| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2020-07-30 19:39:06 +0100 |
|---|---|---|
| committer |   Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2020-09-07 13:16:43 +0300 |
| commit | d1bf5dd8f6d510999b8a12687ee2662e26ab720c (patch) | |
| tree | 978594daafe603eab5fc0db7fa8433405b4121ad /drivers/gpu/drm/i915/gt/intel_ring_submission.c | |
| parent | drm/i915/gem: Delay tracking the GEM context until it is registered (diff) | |
| download | linux-dev-d1bf5dd8f6d510999b8a12687ee2662e26ab720c.tar.xz linux-dev-d1bf5dd8f6d510999b8a12687ee2662e26ab720c.zip | |
drm/i915/gt: Support multiple pinned timelines
We may need to allocate more than one pinned context/timeline for each
engine which can utilise the per-engine HWSP, so we need to give each
a different offset within it.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200730183906.25422-1-chris@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_ring_submission.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 94915f668715..87cef6d01141 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -1250,7 +1250,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine) return -ENODEV; } - timeline = intel_timeline_create(engine->gt, engine->status_page.vma); + timeline = intel_timeline_create_from_engine(engine, + I915_GEM_HWS_SEQNO_ADDR); if (IS_ERR(timeline)) { err = PTR_ERR(timeline); goto err; |