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author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-08 20:45:25 +0100 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-08 20:53:31 +0100 |
commit | cbb153c50ebe4f635d970a1685302288e3f573fe (patch) | |
tree | 26a2b53924c894e3e43d29eab524982427dc85f9 /drivers/gpu/drm/i915/gt/mock_engine.c | |
parent | drm/i915/tgl: Fix the read of the DDI that transcoder is attached to (diff) | |
download | linux-dev-cbb153c50ebe4f635d970a1685302288e3f573fe.tar.xz linux-dev-cbb153c50ebe4f635d970a1685302288e3f573fe.zip |
drm/i915/selftests: Fixup a missing legacy_idx
Grr, missed one*. For using the legacy engine map, we should use
engine->legacy_idx. Ideally, we should know the intel_context in the
selftest and avoid all the fiddling around with unwanted GEM contexts.
* In my defence, the conflict was added in another patch after it was
tested by CI.
v2: mock engines needs legacy love as well
Fixes: f1c4d157ab9b ("drm/i915: Fix up the inverse mapping for default ctx->engines[]")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190808194525.9410-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/gt/mock_engine.c')
-rw-r--r-- | drivers/gpu/drm/i915/gt/mock_engine.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index c64790864795..dd02e59b192f 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -263,6 +263,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, snprintf(engine->base.name, sizeof(engine->base.name), "%s", name); engine->base.id = id; engine->base.mask = BIT(id); + engine->base.instance = id; engine->base.status_page.addr = (void *)(engine + 1); engine->base.cops = &mock_context_ops; @@ -281,6 +282,8 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, timer_setup(&engine->hw_delay, hw_delay_complete, 0); INIT_LIST_HEAD(&engine->hw_queue); + intel_engine_add_user(&engine->base); + return &engine->base; } |