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| author |   Changbin Du <changbin.du@intel.com> | 2018-05-15 10:35:34 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-07-09 10:22:45 +0800 |
| commit | 6fd7937832698e73a5719ff488c2fc5e22c9c0ba (patch) | |
| tree | 528cd385bb4c74bb72e75f46dbf88e0ef1483da1 /drivers/gpu/drm/i915/gvt/gtt.c | |
| parent | drm/i915/gvt: Add new 64K entry type (diff) | |
| download | linux-dev-6fd7937832698e73a5719ff488c2fc5e22c9c0ba.tar.xz linux-dev-6fd7937832698e73a5719ff488c2fc5e22c9c0ba.zip | |
drm/i915/gvt: Add PTE IPS bit operations
Add three IPS operation functions to test/set/clear IPS in PDE.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/gtt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/gtt.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 03f2a5b26546..3e6733914530 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -400,6 +400,22 @@ static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e) return true; } +static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e) +{ + if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY)) + return false; + + return !!(e->val64 & GEN8_PDE_IPS_64K); +} + +static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e) +{ + if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY)) + return; + + e->val64 &= ~GEN8_PDE_IPS_64K; +} + static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) { /* @@ -456,6 +472,8 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = { .set_present = gtt_entry_set_present, .test_present = gen8_gtt_test_present, .test_pse = gen8_gtt_test_pse, + .clear_ips = gen8_gtt_clear_ips, + .test_ips = gen8_gtt_test_ips, .get_pfn = gen8_gtt_get_pfn, .set_pfn = gen8_gtt_set_pfn, }; |