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authorZhao Yan <yan.y.zhao@intel.com>2018-05-08 14:52:42 +0800
committerZhi Wang <zhi.a.wang@intel.com>2018-05-14 05:18:55 +0800
commit0438a1059877396319b90da289f1473c9c973cd8 (patch)
tree84c68706670078b62f18066ffd78bd798a57b5a3 /drivers/gpu/drm/i915/gvt/handlers.c
parentdrm/i915/gvt: let NOPID be the default value of force_to_nonpriv registers (diff)
downloadlinux-dev-0438a1059877396319b90da289f1473c9c973cd8.tar.xz
linux-dev-0438a1059877396319b90da289f1473c9c973cd8.zip
drm/i915/gvt: do not return error on handling force_to_nonpriv registers
Return error will cause vm hang and enter failsafe mode. However, we don't want that happen on detecting an wrong force_to_nonpriv register write. Therefore, we just omit the wrong write or patch it to default value. v2: only return 0 on detecting lri write of registers outside whitelist, but still return error on other error conditions. (zhenyu wang) Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Reviewed-by: Zhang Yulei <yulei.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index bf2fa606afcd..4b6532fb789a 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -495,7 +495,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
vgpu->id, reg_nonpriv, offset);
- return ret;
+ return 0;
}
static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,