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| author |   Matt Roper <matthew.d.roper@intel.com> | 2022-02-14 22:13:41 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-02-16 12:29:47 -0800 |
| commit | 573ca6fb97c617eef263b15d982dac2f85fd2854 (patch) | |
| tree | 2ad284171e50da43ce0d5d8cd570acaccd1281df /drivers/gpu/drm/i915/gvt/handlers.c | |
| parent | drm/i915/gt: Order GT registers by MMIO offset (diff) | |
| download | linux-dev-573ca6fb97c617eef263b15d982dac2f85fd2854.tar.xz linux-dev-573ca6fb97c617eef263b15d982dac2f85fd2854.zip | |
drm/i915: Define MCH registers relative to MCHBAR_MIRROR_BASE
A few of our MCH registers are defined with absolute register offsets.
For consistency, let's switch their definitions to be relative offsets
from MCHBAR_MIRROR_BASE.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220215061342.2055952-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
0 files changed, 0 insertions, 0 deletions