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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-11-12 21:38:08 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-01-26 21:28:42 +0200 |
| commit | 6a6d914de30f15472b2dc36e8ac6bf016cfbaed5 (patch) | |
| tree | bf11d79419fd283ba9069d78d33a6be04eadac92 /drivers/gpu/drm/i915/gvt/handlers.c | |
| parent | drm/i915: Clean up SKL_BOTTOM_COLOR defines (diff) | |
| download | linux-dev-6a6d914de30f15472b2dc36e8ac6bf016cfbaed5.tar.xz linux-dev-6a6d914de30f15472b2dc36e8ac6bf016cfbaed5.zip | |
drm/i915: Clean up PIPECONF bit defines
Use REG_BIT() & co. for PIPECONF bits, and adjust the
naming of various bits to be more consistent.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 9f8ae6776e98..a1f9ab4a4e63 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -702,11 +702,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, data = vgpu_vreg(vgpu, offset); if (data & PIPECONF_ENABLE) { - vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; + vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE; vgpu_update_refresh_rate(vgpu); vgpu_update_vblank_emulation(vgpu, true); } else { - vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; + vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE; vgpu_update_vblank_emulation(vgpu, false); } return 0; |