diff options
| author |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-10-22 13:21:45 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-10-24 10:45:44 +0800 |
| commit | 946260e5fb60fcf3a4fbe77840280b5191300564 (patch) | |
| tree | 6c1ef4e70f73737741880ded9aa4bc262f736f7e /drivers/gpu/drm/i915/gvt/render.c | |
| parent | drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate (diff) | |
| download | linux-dev-946260e5fb60fcf3a4fbe77840280b5191300564.tar.xz linux-dev-946260e5fb60fcf3a4fbe77840280b5191300564.zip | |
drm/i915/gvt: Fix broken mocs offset
Fix missed mocs offset reg setting for save/restore function.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/render.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/render.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index be1a7dfd210b..3af894b3d257 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -177,6 +177,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) if (!IS_SKYLAKE(dev_priv)) return; + offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { gen9_render_mocs[ring_id][i] = I915_READ(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); @@ -214,6 +215,7 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) if (!IS_SKYLAKE(dev_priv)) return; + offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { vgpu_vreg(vgpu, offset) = I915_READ(offset); I915_WRITE(offset, gen9_render_mocs[ring_id][i]); |