diff options
| author |   Colin Xu <colin.xu@intel.com> | 2020-07-09 15:09:57 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2020-07-29 14:18:32 +0800 |
| commit | 9e7c0efadb86ddb58965561bbca638d44792d78f (patch) | |
| tree | 4b0f2f50f22ede6c1961dea82623c27fe0cf54f4 /drivers/gpu/drm/i915/gvt/vgpu.c | |
| parent | drm/i915/gvt: Do not destroy ppgtt_mm during vGPU D3->D0. (diff) | |
| download | linux-dev-9e7c0efadb86ddb58965561bbca638d44792d78f.tar.xz linux-dev-9e7c0efadb86ddb58965561bbca638d44792d78f.zip | |
drm/i915/gvt: Do not reset pv_notified when vGPU transit from D3->D0
Unlike full initialization like normal boot, guest driver won't
pv_notified GVT when vGPU transit from D3->D0. If pv_notified is reset,
later vGPU operations will trigger enter into failsafe mode.
Considering the fact that vGPU will at least notify GVT pv_notified once
before D3/D0 transition, it's safe to skip reset pv_notified in D3->D0.
To test this feature, make sure S3 is enabled in QEMU parameters:
i440fx: PIIX4_PM.disable_s3=0
q35: ICH9-LPC.disable_s3=0
Also need enable sleep option in guest OS if it's disabled.
v2:
- Revise commit message to more accurate description. (Kevin)
- Split patch by logic. (Zhenyu)
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Hang Yuan <hang.yuan@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200709071002.247960-3-colin.xu@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/vgpu.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/vgpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index fb12448fe353..8fa9b31a2484 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -579,13 +579,14 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, intel_vgpu_reset_cfg_space(vgpu); /* only reset the failsafe mode when dmlr reset */ vgpu->failsafe = false; - vgpu->pv_notified = false; /* * PCI_D0 is set before dmlr, so reset d3_entered here * after done using. */ if(vgpu->d3_entered) vgpu->d3_entered = false; + else + vgpu->pv_notified = false; } } |