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| author |   Jordan Justen <jordan.l.justen@intel.com> | 2016-03-06 23:30:30 -0800 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-03-21 10:03:26 +0100 |
| commit | 6cf0716c0321344fdc72205d590e968e53492088 (patch) | |
| tree | 75899e1fd24762d2a0a48c9d63a6bc2958e0b905 /drivers/gpu/drm/i915/i915_cmd_parser.c | |
| parent | drm/i915: Add Haswell CS GPR registers to whitelist (diff) | |
| download | linux-dev-6cf0716c0321344fdc72205d590e968e53492088.tar.xz linux-dev-6cf0716c0321344fdc72205d590e968e53492088.zip | |
drm/i915: Bump command parser version for new whitelisted registers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-6-git-send-email-jordan.l.justen@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_cmd_parser.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_cmd_parser.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 546dfccdf6dd..a337f33bec5b 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void) * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. * 5. GPGPU dispatch compute indirect registers. + * 6. TIMESTAMP register and Haswell CS GPR registers */ - return 5; + return 6; } |