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author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-16 11:38:43 +0000 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-16 20:28:26 +0000 |
commit | f899f786d181e03f6ca29319bd90ba62231cb44b (patch) | |
tree | b2c4ca26b16b1df349ce393c2ab24d82ef36ec36 /drivers/gpu/drm/i915/i915_drv.c | |
parent | drm/i915/gt: Restrict gen7 w/a batch to Haswell (diff) | |
download | linux-dev-f899f786d181e03f6ca29319bd90ba62231cb44b.tar.xz linux-dev-f899f786d181e03f6ca29319bd90ba62231cb44b.zip |
drm/i915: Move GGTT fence registers under gt/
Since the fence registers control HW detiling through the GGTT
aperture, make them a part of the intel_ggtt under gt/
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200316113846.4974-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 480f756bdadc..9327d56dba5a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1288,7 +1288,7 @@ static int i915_drm_resume(struct drm_device *dev) drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); i915_ggtt_resume(&dev_priv->ggtt); - i915_gem_restore_fences(&dev_priv->ggtt); + intel_ggtt_restore_fences(&dev_priv->ggtt); intel_csr_ucode_resume(dev_priv); @@ -1606,7 +1606,7 @@ static int intel_runtime_suspend(struct device *kdev) intel_gt_runtime_resume(&dev_priv->gt); - i915_gem_restore_fences(&dev_priv->ggtt); + intel_ggtt_restore_fences(&dev_priv->ggtt); enable_rpm_wakeref_asserts(rpm); @@ -1687,7 +1687,7 @@ static int intel_runtime_resume(struct device *kdev) * we can do is to hope that things will still work (and disable RPM). */ intel_gt_runtime_resume(&dev_priv->gt); - i915_gem_restore_fences(&dev_priv->ggtt); + intel_ggtt_restore_fences(&dev_priv->ggtt); /* * On VLV/CHV display interrupts are part of the display |