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| author |   Matthew Auld <matthew.auld@intel.com> | 2021-07-23 11:50:44 +0100 |
|---|---|---|
| committer | Matthew Auld <matthew.auld@intel.com> | 2021-07-27 09:16:44 +0100 |
| commit | 3821cc7fc0b90a55c3708628336a97993e464dba (patch) | |
| tree | 80c56c7a30f275b0beaa16bef9671031d86cbd49 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | drm/i915/gem: Migrate to system at dma-buf attach time (v7) (diff) | |
| download | linux-dev-3821cc7fc0b90a55c3708628336a97993e464dba.tar.xz linux-dev-3821cc7fc0b90a55c3708628336a97993e464dba.zip | |
drm/i915: document caching related bits
Try to document the object caching related bits, like cache_coherent and
cache_dirty.
v2(Ville):
- As pointed out by Ville, fix the completely incorrect assumptions
about the "partial" coherency on shared LLC platforms.
v3(Daniel):
- Fix nonsense about "dirtying" the cache with reads.
v4(Daniel):
- Various improvements, including adding some more details for WT.
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723105045.400841-1-matthew.auld@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b83389c06550..5c82a8012332 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -392,15 +392,6 @@ struct drm_i915_display_funcs { void (*read_luts)(struct intel_crtc_state *crtc_state); }; -enum i915_cache_level { - I915_CACHE_NONE = 0, - I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ - I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc - caches, eg sampler/render caches, and the - large Last-Level-Cache. LLC is coherent with - the CPU, but L3 is only visible to the GPU. */ - I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ -}; #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ |