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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2016-08-04 16:32:27 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-08-04 20:19:55 +0100 |
| commit | ad1a7d20a1034ac916b6f73b2e1146920f709eaf (patch) | |
| tree | 0554da04a07e52dfa2e0a2e32c3a1a02c53856f4 /drivers/gpu/drm/i915/i915_gem_tiling.c | |
| parent | drm/i915: Convert 4096 alignment request to 0 for drm_mm allocations (diff) | |
| download | linux-dev-ad1a7d20a1034ac916b6f73b2e1146920f709eaf.tar.xz linux-dev-ad1a7d20a1034ac916b6f73b2e1146920f709eaf.zip | |
drm/i915: Update the GGTT size/alignment query functions
In order to be consistent with other address space functions, we want to
pass around 64-bit sizes, even though all known global GTT are limited
to 4GiB. Similarly, we are trying to be consistent in using the _ggtt_
nomenclature when referring to the special global GTT.
v2: Update docs to consistently state "global GTT".
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470324762-2545-11-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index fa2eb4a4f212..4e42da691e4e 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -133,7 +133,8 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) return false; } - size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); + size = i915_gem_get_ggtt_size(obj->base.dev, + obj->base.size, tiling_mode); if (i915_gem_obj_ggtt_size(obj) != size) return false; |