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| author |   Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> | 2022-06-21 12:21:05 -0700 |
|---|---|---|
| committer |   John Harrison <John.C.Harrison@Intel.com> | 2022-06-27 12:21:22 -0700 |
| commit | 0667429ce68e0b08f9f1fec8fd0b1f57228f605e (patch) | |
| tree | ccea219b1fdacecc254f358db8bcaaca24322596 /drivers/gpu/drm/i915/i915_gpu_error.c | |
| parent | drm/i915/guc: Don't update engine busyness stats too frequently (diff) | |
| download | linux-dev-0667429ce68e0b08f9f1fec8fd0b1f57228f605e.tar.xz linux-dev-0667429ce68e0b08f9f1fec8fd0b1f57228f605e.zip | |
drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.
In addition, extend the WA to gen11.
v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks
v3: (Daneile)
- Drop changes to intel_ring_submission since WA does not apply to it
- Log an error if MSG IDLE is not defined for an engine
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220621192105.2100585-1-umesh.nerlige.ramappa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gpu_error.c')
0 files changed, 0 insertions, 0 deletions