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| author |   Matt Roper <matthew.d.roper@intel.com> | 2021-08-06 10:41:30 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-08-11 13:59:42 -0700 |
| commit | c5589bb5dccb0c5cb74910da93663f489589f3ce (patch) | |
| tree | 563f2ec16df168a38f2459931d8823d40720d451 /drivers/gpu/drm/i915/i915_irq.c | |
| parent | drm/i915/dg2: Configure PCON in DP pre-enable path (diff) | |
| download | linux-dev-c5589bb5dccb0c5cb74910da93663f489589f3ce.tar.xz linux-dev-c5589bb5dccb0c5cb74910da93663f489589f3ce.zip | |
drm/i915: Only access SFC_DONE when media domain is not fused off
The SFC_DONE register lives within the corresponding VD0/VD2/VD4/VD6
forcewake domain and is not accessible if the vdbox in that domain is
fused off and the forcewake is not initialized.
This mistake went unnoticed because until recently we were using the
wrong register offset for the SFC_DONE register; once the register
offset was corrected, we started hitting errors like
<4> [544.989065] i915 0000:cc:00.0: Uninitialized forcewake domain(s) 0x80 accessed at 0x1ce000
on parts with fused-off vdbox engines.
Fixes: e50dbdbfd9fb ("drm/i915/tgl: Add SFC instdone to error state")
Fixes: 82929a2140eb ("drm/i915: Correct SFC_DONE register offset")
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210806174130.1058960-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
0 files changed, 0 insertions, 0 deletions