diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-06-23 16:08:52 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-06-27 18:35:09 +0300 |
| commit | 04155815dbb8320ecd17dd54e85c9a5ae5d63bb9 (patch) | |
| tree | b9335385b833b94cd6b373e47dd8b9f969c0d78f /drivers/gpu/drm/i915/i915_pci.c | |
| parent | drm/i915: Eliminate PIPECONF RMWs from .color_commit() (diff) | |
| download | linux-dev-04155815dbb8320ecd17dd54e85c9a5ae5d63bb9.tar.xz linux-dev-04155815dbb8320ecd17dd54e85c9a5ae5d63bb9.zip | |
drm/i915: Move dbuf details to INTEL_INFO->display
DBUF is a display thing, so move it into the display
portion of the device info.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 1e5c40f36798..b6b7d8eb5b57 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -649,8 +649,8 @@ static const struct intel_device_info chv_info = { .display.has_ipc = 1, \ .display.has_psr = 1, \ .display.has_psr_hw_tracking = 1, \ - .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ - .dbuf.slice_mask = BIT(DBUF_S1) + .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ + .display.dbuf.slice_mask = BIT(DBUF_S1) #define SKL_PLATFORM \ GEN9_FEATURES, \ @@ -685,7 +685,7 @@ static const struct intel_device_info skl_gt4_info = { #define GEN9_LP_FEATURES \ GEN(9), \ .is_lp = 1, \ - .dbuf.slice_mask = BIT(DBUF_S1), \ + .display.dbuf.slice_mask = BIT(DBUF_S1), \ .display.has_hotplug = 1, \ .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ @@ -722,14 +722,14 @@ static const struct intel_device_info skl_gt4_info = { static const struct intel_device_info bxt_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_BROXTON), - .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ + .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ }; static const struct intel_device_info glk_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_GEMINILAKE), .display.ver = 10, - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ + .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ GLK_COLORS, }; @@ -819,8 +819,8 @@ static const struct intel_device_info cml_gt2_info = { }, \ GEN(11), \ ICL_COLORS, \ - .dbuf.size = 2048, \ - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ + .display.dbuf.size = 2048, \ + .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ .display.has_dsc = 1, \ .has_coherent_ggtt = false, \ .has_logical_ring_elsq = 1 @@ -942,8 +942,8 @@ static const struct intel_device_info adl_s_info = { .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ DRM_COLOR_LUT_EQUAL_CHANNELS, \ }, \ - .dbuf.size = 4096, \ - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ + .display.dbuf.size = 4096, \ + .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ BIT(DBUF_S4), \ .display.has_ddi = 1, \ .display.has_dmc = 1, \ |