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| author |   Rafael Antognolli <rafael.antognolli@intel.com> | 2017-11-03 11:30:27 -0700 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-11-08 12:43:17 -0800 |
| commit | 0a60797a0efbc495f514304d83eb289bb55990a6 (patch) | |
| tree | a43c8c06ca3bdc29c73ee3b9c76490af7d522a3c /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Move init_clock_gating() back to where it was (diff) | |
| download | linux-dev-0a60797a0efbc495f514304d83eb289bb55990a6.tar.xz linux-dev-0a60797a0efbc495f514304d83eb289bb55990a6.zip | |
drm/i915: Implement ReadHitWriteOnlyDisable.
The workaround for this is described as:
"if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
Further documentation in the internal bug referenced by the bspec
suggest that any of the above suggestions should suffice to fix the
issue. We are going with disabling RCC clock gating.
Unfortunately, what we are doing doesn't match the name of the
workaround, but at least it matches its description.
This change improves CNL stability by avoiding some of the hangs seen in
the platform.
v2: Only disable RCC clock gating.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171103183027.5051-1-rafael.antognolli@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f0f8f6059652..6ef33422f762 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3837,6 +3837,7 @@ enum { */ #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) #define SARBUNIT_CLKGATE_DIS (1 << 5) +#define RCCUNIT_CLKGATE_DIS (1 << 7) /* * Display engine regs |