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authorKai Vehmanen <kai.vehmanen@linux.intel.com>2019-10-03 11:55:30 +0300
committerJani Nikula <jani.nikula@intel.com>2019-10-04 15:41:31 +0300
commit1580d3cdddbba4a5ef78a04a5289e32844e6af24 (patch)
tree3b162033bc85b170f5717c5ec505f42e0aec73a6 /drivers/gpu/drm/i915/i915_reg.h
parentdrm/i915/dp: remove static variable for aux last status (diff)
downloadlinux-dev-1580d3cdddbba4a5ef78a04a5289e32844e6af24.tar.xz
linux-dev-1580d3cdddbba4a5ef78a04a5289e32844e6af24.zip
drm/i915: Fix audio power up sequence for gen10+ display
On platfroms with gen10+ display, driver must set the enable bit of AUDIO_PIN_BUF_CTL register before transactions with the HDA controller can proceed. Add setting this bit to the audio power up sequence. Failing to do this resulted in errors during display audio codec probe, and failures during resume from suspend. Note: We may also need to disable the bit afterwards, but there are still unresolved issues with that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214 Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191003085531.30990-1-kai.vehmanen@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eefd789b9a28..813ddea3f9f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9133,6 +9133,8 @@ enum {
#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
#define AUD_FREQ_CNTRL _MMIO(0x65900)
+#define AUD_PIN_BUF_CTL _MMIO(0x48414)
+#define AUD_PIN_BUF_ENABLE REG_BIT(31)
/*
* HSW - ICL power wells