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| author |   Praveen Paneri <praveen.paneri@intel.com> | 2017-08-11 00:00:33 +0530 |
|---|---|---|
| committer |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2017-08-25 21:13:33 -0300 |
| commit | 5654a1623c8717c40384b1b79251b4d9dd73b751 (patch) | |
| tree | a1b2fbfd6a64b5040e72a91d55381059c40b8c49 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/cnl: don't hardcode DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT (diff) | |
| download | linux-dev-5654a1623c8717c40384b1b79251b4d9dd73b751.tar.xz linux-dev-5654a1623c8717c40384b1b79251b4d9dd73b751.zip | |
drm/i915: Fix FBC cfb stride programming for non X-tiled FB
When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as
cfb_stride = ceiling[(at least plane width in pixels)/
(32 * compression limit factor)] * 8
v2: Minor fix for a build error
v3: Fixed subject, register name and platform check (Ville)
v4: Added WA details in comment (Paulo)
v5:
- Read modified reg write to preserve other bit values (Paulo)
- Store modified stride value in reg_params (Paulo)
- Keep GLK out of the WA (Paulo)
v6:
- added additional field in reg_params for gen9_wa_cfb_stride (Paulo)
- Used appropriate bit mask while writing the register (Paulo)
v7 (from Paulo):
- Fix coding style and spacing issues.
- Mask the old values before writing.
- Bikeshed comments and unnecessary checks.
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1502389833-32621-1-git-send-email-praveen.paneri@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c59c590e45c4..e2908ae34004 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6923,6 +6923,10 @@ enum { #define GLK_CL1_PWR_DOWN (1 << 11) #define GLK_CL0_PWR_DOWN (1 << 10) +#define CHICKEN_MISC_4 _MMIO(0x4208c) +#define FBC_STRIDE_OVERRIDE (1 << 13) +#define FBC_STRIDE_MASK 0x1FFF + #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 #define HSW_FBCQ_DIS (1 << 22) |