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| author |   José Roberto de Souza <jose.souza@intel.com> | 2019-06-19 16:31:34 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-06-20 13:18:04 -0700 |
| commit | 683d672c425aa29c0e74583ed28a0e011cc0bb43 (patch) | |
| tree | f2a91961be3d24bd2a2c09545aab6bd49ccc9593 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/ehl/dsi: Set lane latency optimization for DW1 (diff) | |
| download | linux-dev-683d672c425aa29c0e74583ed28a0e011cc0bb43.tar.xz linux-dev-683d672c425aa29c0e74583ed28a0e011cc0bb43.zip | |
drm/i915/ehl/dsi: Enable AFE over PPI strap
The other additional step in the DSI sequence for EHL.
v2:
- Using REG_BIT()(Matt)
- Fixed commit message typo(Vandita)
BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 969c3b23d519..6ccc713d85b3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1993,6 +1993,10 @@ enum i915_power_well_id { #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) +#define _ICL_DPHY_CHKN_REG 0x194 +#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) + #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) |