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| author |   Michał Winiarski <michal.winiarski@intel.com> | 2019-09-26 12:06:33 +0200 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-09-26 22:11:04 +0100 |
| commit | 74b2089a105f43c33d2f2124bd03d1085fe7c9fc (patch) | |
| tree | ac3263f213fc170e682a6f28caa0077ff9363cec /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/perf: Fix use of kernel-doc format in structure members (diff) | |
| download | linux-dev-74b2089a105f43c33d2f2124bd03d1085fe7c9fc.tar.xz linux-dev-74b2089a105f43c33d2f2124bd03d1085fe7c9fc.zip | |
drm/i915: Add definitions for MI_MATH command
We can use it in i915 for updating parts of unmasked registers from
within a batch. We're also adding Gen8+ versions of CS_GPR registers
(aka MI_MATH_REG in the coprocessor).
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190926100635.9416-4-michal.winiarski@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e752de9470bd..5e30f1a14624 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2483,6 +2483,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ +/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ +#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) +#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) + #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) |