diff options
| author |   Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> | 2021-07-23 10:42:37 -0700 |
|---|---|---|
| committer |   Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 09:32:54 -0700 |
| commit | 7711749a604996a41e14b66e3163e045a89fe8e1 (patch) | |
| tree | 1f18746b185f82e886f2398c7edbe7d401241c05 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/dg2: Wait for SNPS PHY calibration during display init (diff) | |
| download | linux-dev-7711749a604996a41e14b66e3163e045a89fe8e1.tar.xz linux-dev-7711749a604996a41e14b66e3163e045a89fe8e1.zip | |
drm/i915/dg2: Update lane disable power state during PSR
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-29-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7306832921f8..51301fa9da14 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2332,6 +2332,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188) #define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27) +#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200) +#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30) + #define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300) #define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18) #define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10) |