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| author |   Matt Roper <matthew.d.roper@intel.com> | 2021-11-16 09:48:15 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-12-02 21:40:26 -0800 |
| commit | 7cbea1b61788c05a5bcb84c73ed5ed90bb2e0a93 (patch) | |
| tree | f21cdf1b0121192d4b11cd70fa0d563a001edc34 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/dg2: s/DISP_STEPPING/DISPLAY_STEPPING/ (diff) | |
| download | linux-dev-7cbea1b61788c05a5bcb84c73ed5ed90bb2e0a93.tar.xz linux-dev-7cbea1b61788c05a5bcb84c73ed5ed90bb2e0a93.zip | |
drm/i915/dg2: Add Wa_14010547955
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-3-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 47fcd104868f..159231136d70 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8483,8 +8483,9 @@ enum { _PIPEB_CHICKEN) #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) -#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) -#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) #define FF_MODE2 _MMIO(0x6604) #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) |