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| author |   Imre Deak <imre.deak@intel.com> | 2018-07-09 18:24:27 +0300 |
|---|---|---|
| committer |   Jon Bloomfield <jon.bloomfield@intel.com> | 2019-11-05 11:43:07 -0800 |
| commit | 7e34f4e4aad3fd34c02b294a3cf2321adf5b4438 (patch) | |
| tree | 309a2f84fac09bf9e294dbeb4dd49d6c1d71ce48 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Lower RM timeout to avoid DSI hard hangs (diff) | |
| download | linux-dev-7e34f4e4aad3fd34c02b294a3cf2321adf5b4438.tar.xz linux-dev-7e34f4e4aad3fd34c02b294a3cf2321adf5b4438.zip | |
drm/i915/gen8+: Add RC6 CTX corruption WA
In some circumstances the RC6 context can get corrupted. We can detect
this and take the required action, that is disable RC6 and runtime PM.
The HW recovers from the corrupted state after a system suspend/resume
cycle, so detect the recovery and re-enable RC6 and runtime PM.
v2: rebase (Mika)
v3:
- Move intel_suspend_gt_powersave() to the end of the GEM suspend
sequence.
- Add commit message.
v4:
- Rebased on intel_uncore_forcewake_put(i915->uncore, ...) API
change.
v5: rebased on gem/gt split (Mika)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9b76d63cc1ac..f8ee9aba3955 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -471,6 +471,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) +#define GEN8_RC6_CTX_INFO _MMIO(0x8504) + #define GAC_ECO_BITS _MMIO(0x14090) #define ECOBITS_SNB_BIT (1 << 13) #define ECOBITS_PPGTT_CACHE64B (3 << 8) |