diff options
| author |   Matt Roper <matthew.d.roper@intel.com> | 2021-07-23 10:42:33 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 09:06:01 -0700 |
| commit | 865b73ea18bbbb4da4be61186354aaca89d31303 (patch) | |
| tree | bb8e7a19194c446efdd738d5dbe1b364e38f4aef /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/dg2: Add MPLLB programming for SNPS PHY (diff) | |
| download | linux-dev-865b73ea18bbbb4da4be61186354aaca89d31303.tar.xz linux-dev-865b73ea18bbbb4da4be61186354aaca89d31303.zip | |
drm/i915/dg2: Add MPLLB programming for HDMI
At the moment we don't have a proper algorithm that can be used to
calculate PHY settings for arbitrary HDMI link rates. The PHY tables
here should support the regular modes of real-world HDMI monitors.
Bspec: 54032
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-25-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bf4a816995dc..f82a7e24b5cc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2317,12 +2317,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014) #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31) +#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30) #define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10) #define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018) #define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11) #define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C) +#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18) +#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15) #define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12) #define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0) |