diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-03-05 13:05:47 +0200 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-05 21:30:44 +0100 |
| commit | 8f670bb15a69e1186098454beb1b43dc1d923a24 (patch) | |
| tree | 175f076b4559206efa56e321ca74c165950f0ab7 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Use RMW to update chicken bits in gen7_enable_fbc() (diff) | |
| download | linux-dev-8f670bb15a69e1186098454beb1b43dc1d923a24.tar.xz linux-dev-8f670bb15a69e1186098454beb1b43dc1d923a24.zip | |
drm/i915: Unify CHICKEN_PIPESL_1 register definitions
We have two names for the same register CHICKEN_PIPESL_1 and
HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.
Also rename the FBCQ disable bit to resemble the name we've
given to a similar bit on earlier platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c913ca5c3b39..04c00f39e94a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1129,13 +1129,6 @@ #define FBC_REND_NUKE (1<<2) #define FBC_REND_CACHE_CLEAN (1<<1) -#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 -#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 -#define HSW_BYPASS_FBC_QUEUE (1<<22) -#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ - _HSW_PIPE_SLICE_CHICKEN_1_A, + \ - _HSW_PIPE_SLICE_CHICKEN_1_B) - /* * GPIO regs */ @@ -4148,7 +4141,8 @@ #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 -#define DPRS_MASK_VBLANK_SRD (1 << 0) +#define HSW_FBCQ_DIS (1 << 22) +#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) #define DISP_ARB_CTL 0x45000 |