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| author |   Lucas De Marchi <lucas.demarchi@intel.com> | 2020-07-13 11:23:19 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2020-07-14 02:47:19 -0700 |
| commit | 97b492f5f98357c5238d74b1070d42c5fe4ac75d (patch) | |
| tree | 21fe613c22fc22fe04f2e939c6e63ae1d9cbf66f /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/dg1: Add DG1 PCI IDs (diff) | |
| download | linux-dev-97b492f5f98357c5238d74b1070d42c5fe4ac75d.tar.xz linux-dev-97b492f5f98357c5238d74b1070d42c5fe4ac75d.zip | |
drm/i915/dg1: add support for the master unit interrupt
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
v2: fix coding style on register definition
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200713182321.12390-4-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 86a23ced051b..4e796ff4d7d0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7733,6 +7733,10 @@ enum { #define GEN11_GT_DW1_IRQ (1 << 1) #define GEN11_GT_DW0_IRQ (1 << 0) +#define DG1_MSTR_UNIT_INTR _MMIO(0x190008) +#define DG1_MSTR_IRQ REG_BIT(31) +#define DG1_MSTR_UNIT(u) REG_BIT(u) + #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) #define GEN11_AUDIO_CODEC_IRQ (1 << 24) |