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| author |   Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2019-10-15 18:44:43 +0300 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-15 18:17:34 +0100 |
| commit | 99739f9431f9fa8b4706dfa4c99389b400b8af23 (patch) | |
| tree | f699df7af32b5cb3f090b8c84d4c3c93abc0a353 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/tgl: Add extra hdc flush workaround (diff) | |
| download | linux-dev-99739f9431f9fa8b4706dfa4c99389b400b8af23.tar.xz linux-dev-99739f9431f9fa8b4706dfa4c99389b400b8af23.zip | |
drm/i915/tgl: Keep FF dop clock enabled for A0
To ensure correct state data for compute workloads, we
need to keep the ff dop clock enabled.
References: HSDES#1606700617
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-5-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 821159c4cd32..4b58861b5114 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7673,6 +7673,7 @@ enum { #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) +#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) #define GEN8_CS_CHICKEN1 _MMIO(0x2580) #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) |