diff options
| author |   Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2019-10-25 15:17:18 +0300 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-25 18:29:05 +0100 |
| commit | ba1d18e386d991356f59bbb417b0c642abf671fa (patch) | |
| tree | bef606309697d880deb8f4f6196403a77e98a748 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Fix PCH reference clock for FDI on HSW/BDW (diff) | |
| download | linux-dev-ba1d18e386d991356f59bbb417b0c642abf671fa.tar.xz linux-dev-ba1d18e386d991356f59bbb417b0c642abf671fa.zip | |
drm/i915: capture aux page table error register
TGL introduced a feature in which we map the main surface to the
auxiliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
[ickle: Be brave and apply to gen12]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025121718.18806-1-lionel.g.landwerlin@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fd3d2de59101..746326784a4d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2603,6 +2603,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define FAULT_VA_HIGH_BITS (0xf << 0) #define FAULT_GTT_SEL (1 << 4) +#define GEN12_AUX_ERR_DBG _MMIO(0x43f4) + #define FPGA_DBG _MMIO(0x42300) #define FPGA_DBG_RM_NOCLAIM (1 << 31) |