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| author |   Mahesh Kumar <mahesh1.kumar@intel.com> | 2018-10-15 19:37:52 -0700 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-10-16 09:01:01 -0700 |
| commit | bb1c7edc6d4d5cc6917814d858d47b22d2e93cde (patch) | |
| tree | c77c9e654d12b7d35514f9325d19db1a46efb9cd /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/icl: Introduce new macros to get combophy registers (diff) | |
| download | linux-dev-bb1c7edc6d4d5cc6917814d858d47b22d2e93cde.tar.xz linux-dev-bb1c7edc6d4d5cc6917814d858d47b22d2e93cde.zip | |
drm/i915/icl: Fix DDI/TC port clk_off bits
DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
from offset 12 & TC4 is at offset 21.
Create a function to choose correct clk-off bit.
v2: Add fixes tag (Lucas)
Fixes: c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks")
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016023752.9285-1-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fa8b52743bd9..81f1c601987d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9319,6 +9319,9 @@ enum skl_power_gate { #define DPCLKA_CFGCR0_ICL _MMIO(0x164280) #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ (port) + 10)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10)) +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ + 21 : (tc_port) + 12)) #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ (port) * 2) #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) |