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| author |   Animesh Manna <animesh.manna@intel.com> | 2019-12-05 18:05:13 +0530 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2019-12-11 12:13:47 +0200 |
| commit | d04a661a2c7169b48782aa5e9d85d4b4383d562e (patch) | |
| tree | b3e7fd88475fed570d061b1fc8bba16f25f7a75f /drivers/gpu/drm/i915/i915_reg.h | |
| parent | Merge drm/drm-next into drm-intel-next-queued (diff) | |
| download | linux-dev-d04a661a2c7169b48782aa5e9d85d4b4383d562e.tar.xz linux-dev-d04a661a2c7169b48782aa5e9d85d4b4383d562e.zip | |
drm/i915/dsb: Fix in mmio offset calculation of DSB instance
As the current usage is restricted to first DSB instance per pipe, so
existing code could not catch the issue to calculate the mmio offset
of different DSB instance per pipe. Corrected the offset calculation.
Fixes: a6e58d9a2e04 ("drm/i915/dsb: Check DSB engine status.")
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191205123513.22603-1-animesh.manna@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 082190c2dc48..17f9dd3bda72 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12084,7 +12084,7 @@ enum skl_power_gate { /* This register controls the Display State Buffer (DSB) engines. */ #define _DSBSL_INSTANCE_BASE 0x70B00 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ - (pipe) * 0x1000 + (id) * 100) + (pipe) * 0x1000 + (id) * 0x100) #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) |