diff options
| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-11-10 16:03:19 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-11-14 08:47:25 -0800 |
| commit | df49ec8223050d510bd243d85c51139fc101029f (patch) | |
| tree | 3169a7be5dc6c3e69a0d1f15d783ae917ece1c7e /drivers/gpu/drm/i915/i915_reg.h | |
| parent | Merge airlied/drm-next into drm-intel-next-queued (diff) | |
| download | linux-dev-df49ec8223050d510bd243d85c51139fc101029f.tar.xz linux-dev-df49ec8223050d510bd243d85c51139fc101029f.zip | |
drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glk
Display is not sending a PMRsp when a PMReq is received
at the same time that all planes are turned off.
State machine in the dcprunit is stuck in the WAIT4DONE
state which means that there is no fill_done.
WA: disable arbiter clock gating, set bit [27] of 0x46530
v2: As Ville pointed out, based on the description the issue
can happen when disabling the planes, similar to
WaRsPkgCStateDisplayPMReq:hsw
Also description of the issue was updated on commit
message to make it more clear that we need this
earlier.
v3: Restore comment about possibility to system hang
to where we are sure about it, without speculation. (Ville).
v4: Remove doubled sob. Actually do v3 changes :/
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171111000319.5040-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d7e24426120d..cfdf4f821ac3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3852,6 +3852,7 @@ enum { * GEN9 clock gating regs */ #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) +#define DARBF_GATING_DIS (1 << 27) #define PWM2_GATING_DIS (1 << 14) #define PWM1_GATING_DIS (1 << 13) |