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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-09 18:49:47 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-18 22:38:50 +0200 |
| commit | f8a1cb3ff4397c2a295712953452946b3dff70c8 (patch) | |
| tree | 9eb34fe33a61ea2427abe138448e78f73ac15c39 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Fix PSF GV point mask when SAGV is not possible (diff) | |
| download | linux-dev-f8a1cb3ff4397c2a295712953452946b3dff70c8.tar.xz linux-dev-f8a1cb3ff4397c2a295712953452946b3dff70c8.zip | |
drm/i915: Unconfuses QGV vs. PSF point masks
Use separate bitmasks for QGV vs. PSF GV points during
the computation. Makes the whole thing a lot less confusing.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309164948.10671-8-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 56042d363a15..ac6b5c741289 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6720,9 +6720,10 @@ #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe #define ICL_PCODE_POINTS_RESTRICTED 0x0 #define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf -#define ADLS_PSF_PT_SHIFT 8 #define ADLS_QGV_PT_MASK REG_GENMASK(7, 0) +#define ADLS_QGV_PT(x) REG_FIELD_PREP(ADLS_QGV_PT_MASK, (x)) #define ADLS_PSF_PT_MASK REG_GENMASK(10, 8) +#define ADLS_PSF_PT(x) REG_FIELD_PREP(ADLS_PSF_PT_MASK, (x)) #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 #define ICL_PCODE_EXIT_TCCOLD 0x12 |