diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-07 22:21:46 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-08 14:32:29 +0200 |
| commit | 73a116be688041149bbdd1f0ba25da5c4c78a306 (patch) | |
| tree | c79186e5eddc10f651eaaa49c10d30a6698060a1 /drivers/gpu/drm/i915/intel_color.c | |
| parent | drm/i915: Disable pipe gamma when C8 pixel format is used (diff) | |
| download | linux-dev-73a116be688041149bbdd1f0ba25da5c4c78a306.tar.xz linux-dev-73a116be688041149bbdd1f0ba25da5c4c78a306.zip | |
drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()
On g4x+ we depend on the primary plane DSPCNTR gamma/csc enable
bits for the pipe bottom color. To guarantee that those are
correct already when enabling the crtc let's do an explicit
->disable_plane() call before enabling the pipe.
On skl+ this will be handled by the explicit PIPE_BOTTOM_COLOR
register which is already part of the normal color commit we
do durign crtc enable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-8-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_color.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_color.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 09888cc2c134..c0e2806febf6 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -663,6 +663,10 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) intel_atomic_get_old_crtc_state(state, crtc); struct intel_plane *plane; + if (!new_crtc_state->base.active || + drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) + return 0; + if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable && new_crtc_state->csc_enable == old_crtc_state->csc_enable) return 0; |