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| author |   Matt Roper <matthew.d.roper@intel.com> | 2018-12-12 11:17:20 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2018-12-12 12:25:16 -0800 |
| commit | 25db2eaf1097ff6b9169d288e9532072069adb7c (patch) | |
| tree | bab345f1d3690f21fcb848c2c73cd4d643221816 /drivers/gpu/drm/i915/intel_crt.c | |
| parent | drm/i915: DFSM pipe disable is valid from gen9 onwards (v2) (diff) | |
| download | linux-dev-25db2eaf1097ff6b9169d288e9532072069adb7c.tar.xz linux-dev-25db2eaf1097ff6b9169d288e9532072069adb7c.zip | |
drm/i915: Don't forget to reset blocks when testing lower wm levels
During DDB allocation, we try to distribute enough blocks for each plane
to hit the highest watermark level; if that fails, we retry each lower
level (which should require fewer blocks) until we find one that's
possible (or until the whole commit is rejected as impossible). We need
to reset our running block count when trying each lower level, otherwise
all lower levels will fail as well.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: d8e8749802 ("drm/i915: Switch to level-based DDB allocation algorithm (v5)")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212191720.3706-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
0 files changed, 0 insertions, 0 deletions